# HG changeset patch
# User Piotr Sikora <piotr@aviatrix.com>
# Date 1708977640 0
# Mon Feb 26 20:00:40 2024 +0000
# Branch patch015
# Node ID f58bc1041ebca635517b919d58b49923bf24f76d
# Parent 570e97dddeeddb79c71587aa8a10150b64404beb
macOS: detect cache line size at runtime.

Notably, Apple Silicon CPUs have 128 byte cache line size,
which is twice the default configured for generic aarch64.

Signed-off-by: Piotr Sikora <piotr@aviatrix.com>

diff -r 570e97dddeed -r f58bc1041ebc src/os/unix/ngx_darwin_init.c
--- a/src/os/unix/ngx_darwin_init.c Mon Feb 26 20:00:38 2024 +0000
+++ b/src/os/unix/ngx_darwin_init.c Mon Feb 26 20:00:40 2024 +0000
@@ -11,6 +11,7 @@

char ngx_darwin_kern_ostype[16];
char ngx_darwin_kern_osrelease[128];
+int64_t ngx_darwin_hw_cachelinesize;
int ngx_darwin_hw_ncpu;
int ngx_darwin_kern_ipc_somaxconn;
u_long ngx_darwin_net_inet_tcp_sendspace;
@@ -44,6 +45,10 @@


sysctl_t sysctls[] = {
+ { "hw.cachelinesize",
+ &ngx_darwin_hw_cachelinesize,
+ sizeof(ngx_darwin_hw_cachelinesize), 0 },
+
{ "hw.ncpu",
&ngx_darwin_hw_ncpu,
sizeof(ngx_darwin_hw_ncpu), 0 },
@@ -155,6 +160,7 @@
return NGX_ERROR;
}

+ ngx_cacheline_size = ngx_darwin_hw_cachelinesize;
ngx_ncpu = ngx_darwin_hw_ncpu;

if (ngx_darwin_kern_ipc_somaxconn > 32767) {
diff -r 570e97dddeed -r f58bc1041ebc src/os/unix/ngx_posix_init.c
--- a/src/os/unix/ngx_posix_init.c Mon Feb 26 20:00:38 2024 +0000
+++ b/src/os/unix/ngx_posix_init.c Mon Feb 26 20:00:40 2024 +0000
@@ -51,7 +51,10 @@
}

ngx_pagesize = getpagesize();
- ngx_cacheline_size = NGX_CPU_CACHE_LINE;
+
+ if (ngx_cacheline_size == 0) {
+ ngx_cacheline_size = NGX_CPU_CACHE_LINE;
+ }

for (n = ngx_pagesize; n >>= 1; ngx_pagesize_shift++) { /* void */ }

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