Hello,

64 bytes should be the minimum size.

However, A53 is a small segment of arm64 based servers .
Multiple aarch64 based servers uses 128 byte cache lines.
For e.g Centriq 2400 aarch64 server from Qualcomm Datacenter Technologies uses 128 bytes cache line.

To be very accurate , we may read the dcache line size from CTR_EL0 register.
Let me know what you think.

Thanks
Debayan

-----Original Message-----
From: Maxim Dounin [mailto:mdounin@mdounin.ru]
Sent: Friday, December 8, 2017 8:47 PM
To: nginx-devel@nginx.org
Cc: debayang.qdt <debayang.qdt@qualcommdatacenter.com>
Subject: Re: [PATCH] Configure: Fix cacheline size for aarch64 platforms

Hello!

On Fri, Dec 08, 2017 at 02:34:01PM +0530, Debayan Ghosh wrote:

> # HG changeset patch
> # User Debayan Ghosh <debayang.qdt@qualcommdatacenter.com>
> # Date 1512723685 -19800
> # Fri Dec 08 14:31:25 2017 +0530
> # Node ID 51870787e3f3bd8dcffab3b5d43f59ca3660e875
> # Parent 8b84d60ef13db20bae9141849e0e12ff23bc3bbc
> Configure: Fix cacheline size for aarch64 platforms
>
> Currently the default cpu cacheline is set to 32 which is not
> appropriate for aarch64 platforms
>
> diff -r 8b84d60ef13d -r 51870787e3f3 auto/os/conf
> --- a/auto/os/conf Tue Nov 28 12:00:24 2017 +0300
> +++ b/auto/os/conf Fri Dec 08 14:31:25 2017 +0530
> @@ -110,6 +110,11 @@
> NGX_MACH_CACHE_LINE=64
> ;;
>
> + aarch64 )
> + have=NGX_ALIGNMENT value=16 . auto/define
> + NGX_MACH_CACHE_LINE=128
> + ;;
> +
> *)
> have=NGX_ALIGNMENT value=16 . auto/define
> NGX_MACH_CACHE_LINE=32

Any reasons to use 128?

At least for Cortex-A53 Wikipedia lists 64 bytes, see https://en.wikipedia.org/wiki/ARM_Cortex-A53.

--
Maxim Dounin
http://mdounin.ru/
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