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[PATCH] Add support cache line size for Hygon Dhyana CPU

Jinke Fan
May 07, 2019 03:28AM
# HG changeset patch
# User Fanjinke <fanjinke@hygon.cn>
# Date 1557209225 -28800
# Tue May 07 14:07:05 2019 +0800
# Node ID 9bc6da16b217ce2c5fc63048a705c2b3195d3bb7
# Parent 16a1adadf43751f59257ba419f6bacd530dd19d3
Add support cache line size for Hygon Dhyana CPU

Background:
Chengdu Haiguang IC Design Co., Ltd (Hygon) is a Joint Venture between
AMD and Haiguang Information Technology Co.,Ltd., aims at providing high
performance x86 processor for China server market. Its first generation
processor codename is Dhyana, which originates from AMD technology and
shares most of the architecture with AMD's family 17h, but with different
CPU Vendor ID("HygonGenuine")/Family series number(Family 18h).

diff -r 16a1adadf437 -r 9bc6da16b217 src/core/ngx_cpuinfo.c
--- a/src/core/ngx_cpuinfo.c Wed Apr 24 16:38:56 2019 +0300
+++ b/src/core/ngx_cpuinfo.c Tue May 07 14:07:05 2019 +0800
@@ -124,6 +124,8 @@

} else if (ngx_strcmp(vendor, "AuthenticAMD") == 0) {
ngx_cacheline_size = 64;
+ } else if (ngx_strcmp(vendor, "HygonGenuine") == 0) {
+ ngx_cacheline_size = 64;
}
}

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Subject Author Views Posted

[PATCH] Add support cache line size for Hygon Dhyana CPU

Jinke Fan 175 May 07, 2019 03:28AM

Re: [PATCH] Add support cache line size for Hygon Dhyana CPU

Maxim Dounin 58 May 08, 2019 12:10PM

Re: [PATCH] Add support cache line size for Hygon Dhyana CPU

Jinke Fan 94 May 08, 2019 11:38PM



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